Teledyne LeCroy USBTracer_Trainer - Users Manual - Manual (Page 16)

Chapter 1: Overview USB Protocol Suite User Manual
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LeCroy Corporation
1.1.2 Accurate Time Measurement (Voyager, Advisor T3)
The internal counter/timer circuitry enables reliable, accurate (2 ns resolution)
time stamping of recorded bus traffic. Traces and measurement and analysis functions
display this timing information. Time fields are time stamps, idle times, bit times, or time
deltas, in either decimal or hexadecimal format. You can add any number of markers to
denote specific packets, you can make further timing measurements from one marker to
another or from marker to trigger.
An essential feature of time management is that idle traffic does not consume Analyzer
memory. Because of this unique technology, the system can make accurate timing
calculations while still preserving valuable recording memory for important bus traffic.
The oscillator has 2.5 ppm accuracy.
1.1.3 CrossSync Control Panel (Voyager, Advisor T3)
The LeCroy CrossSync control panel provides synchronization for complete end-to-end
visibility into multi-protocol systems.
CrossSync is LeCroy’s analyzer synchronization solution that enables time-aligned
display of protocol traffic from multiple daisy-chained analyzers showing packet traffic
from multiple high-speed serial busses. A lightweight software control panel allows users
to select analyzers for synchronization and manage the recording process. Captured
traffic is displayed using the latest analyzer software (in separate windows) with all the
protocol specific search and reporting features.
Captured packets are displayed in separate windows that share a common time scale.
Navigating the traffic in either direction will scroll to the same timestamp in a
synchronized window. When using the CrossSync option, users can access the full
complement of analysis capabilities available within the individual LeCroy software.
Search, reporting, and decoding all operate normally.
This feature is available with the LeCroy USB Protocol Suite application.
1.1.4 Comprehensive Error Detection and Analysis
The system detects, and alerts you to, every potential bus error and protocol violation,
and their combinations. The Analyzer BusEngine™ circuitry performs real-time triggering
on multiple error conditions, such as PID bad, bit stuffing bad, header or data CRC bad,
end-of-packet bad, babble, activity loss, frame length violation, time-out or turn-around
violation, and data toggle violation. The Analyzer program highlights all
hardware-detected errors and further examines the trace file for additional
protocol errors, including wrong packet length, data payload violation, and
packet termination not on a byte boundary.