NEC PD75402A - Manual (Page 94)

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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS
5.5.4 Operation-Halted Mode
The operation-halted mode is used when no serial transfer is performed, allowing power dissipation to be
reduced.
In this mode, the shift register does not perform shift operations and can be used as an ordinary 8-bit register.
When the RESET signal is input the operation-halted mode is set. The P02/SO/SB0 and P03/SI pins are fixed as
input ports. P01/SCK can be used as an input port depending on the setting of the serial operating mode register.
(1) Register setting
Operation-halted mode setting is performed by the serial operating mode register (CSIM) (see 5.5.3 (1)“Serial
operating mode register” for full details of CSIM).
CSIM is manipulated by 8-bit memory manipulation instructions, but bit manipulation of CSIE is also possible.
Manipulation is also possible using bit names.
Reset input clears this register to 00H.
The shaded area indicates bits used in the operation-halted mode.
Serial Clock Celection Bit (W)*
Serial Interface Operating Mode Selection Bit (W)
Wake-up Function Specification Bit (w)
Match Signal from Address Comparator (R)
Serial Interface Operation Enable/Disable Specification Bit (W)
Shift Register
Operation
Serial Clock
Counter
IRQCSI Flag SO/SB0 & SI Pins
Shift operation
disabled
0 CSIE Cleared Retained Port o function only
* Allow selection of P01/SCK pin status.
Remarks (R) Read only
(W) Write only
Serial interface operation enable/disable specification bit (W)
Address 7 6 5 4 3 2 1 0 Symbol
FE0H CSIE C0I WUP 0 CSIM3 0 CSIM1 0 CSIM