NEC PD75402A - Manual (Page 64)

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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS
5.1.6 Digital Input/Output Port Input/Output Timing
The timing for outputting data to the output latch and fetching pin data or output latch data onto the internal bus
is shown in Fig. 5-9.
Fig. 5-9 Digital Input/Output Port Input/Output Timing
(a) Data fetch by 1-machine-cycle instruction
(b) Data fetch by 2-machine-cycle instruction
(c) Data latching by 1-machine-cycle instruction
(d) Data latching by 2-machine-cycle instruction
1-Machine Cycles
Manipulation
Instruction
Input Timing
Instruction
Execution
2-Machine Cycles
Manipulation Instruction
Instruction
Execution
Input Timing
Manipulation Instruction
Instruction
Execution
Output Latch
(Output Pin)
3
Φ
0
Φ
1
Φ
Manipulation Instruction
Instruction
Execution
Output Latch
(Output Pin)
0
Φ
1
Φ