NEC PD75402A - Manual (Page 140)

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CHAPTER 6. INTERRUPT FUNCTIONS
Interrupt Request Flag
IRQBT
IRQ0
IRQCSI
IRQ2
6.3 INTERRUPT CONTROL CIRCUIT HARDWARE
(1) Interrupt request flag & interrupt enable flag
There are four interrupt request flags (IRQ
×××
) corresponding to the interrupt sources (interrupt: 3, test: 1) as
follows.
INT0 interrupt request flag (IRQ0)
INT2 interrupt request flag (IRQ2)
BT interrupt request flag (IRQBT)
Serial interface interrupt request flag (IRQCSI)
An interrupt request flag is set (1) by generation of an interrupt request and cleared (0) automatically by execution
of an interrupt service.
There are four interrupt enable flags (IE
×××
) corresponding to the interrupt request flags as follows.
INT0 interrupt enable flag (IE0)
INT2 interrupt enable flag (IE2)
BT interrupt enable flag (IEBT)
Serial interface interrupt enable flag (IECSI)
An interrupt enable flag enables an interrupt when its contents are “1” and disables it when 0.
When an interrupt request flag is set and the interrupt enable flag permits an interrupt, a vectored interrupt
request (VRQn) is generated. This signal is also used to release standby mode (HALT mode) (with the exception of
VRQ2).
The interrupt request flags and interrupt enable flags are manipulated by bit-handling instructions and 4-bit
memory handling instructions. In addition, the interrupt enable flags are manipulated by the EI IE
×××
instruction
and the DI IE
×××
instruction. The SKTCLR is normally used for interrupt request flag testing.
Example EI IE0 ; INT0 enabled
DI IEBT ; INTBT disabled
SKTCLR IRQCSI ; Skip and clear if IRQCSI is 1
When the interrupt request flag is set by an instruction, although no interrupt is generated, a vectored interrupt
is executed in the same way as when an interrupt is generated.
With a RESET input, the interrupt request flags and interrupt enable flags are cleared (0) and all interrupts are
disabled.
Table 6-2 Interrupt Request Flag Setting Signal
Interrupt Request Flag Setting Signal
Set by basic time interval signal from basic interval timer.
Set by INT0/P10 pin input signal edge detection. Detected
edge is selected by INT0 mode register (IM0).
Set by serial interface serial data transfer operation
termination signal.
Set by INT2/P12 pin input signal rising edge detection.
Interrupt Enable Flag
IEBT
IE0
IECSI
IE2