NEC PD75402A - Manual (Page 57)

46
CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS
Fig. 5-5 Configuration of Port 5
Pull-Up Resistors
(Mask Option;
µ
PD75402A
Only)
5.1.2 Input/Output Mode Setting
The input/output mode for each input/output port is set by a port mode register as shown in Fig. 5-6. For port
3, input/output can be specified bit by bit by port mode register group A (PMGA). Input/output is specified in 4-bit
units by PMGB for ports 2 and 5, and by PMGA for port 6.
Each port operates as an input port when the corresponding port mode register bit is “0”, and as an output port
when “1”.
Since, when output mode is selected by setting the port mode register, the output latch contents are simulta-
neously output to the output pin, the output latch contents must be overwritten in advance with the required value
before output mode is set.
Port mode register group A and B are each set by an 8-bit memory handling instruction.
With a RESET input, all bits of each port mode register are cleared to zero, and thus the output buffer is turned
off and all ports are set to input mode.
Internal Bus
Output Latch
PM5
PMGB
Bit 5
N-ch
Open-Drain
Output
Buffer
P50
P51
P52
P53
PM5=1
PM5=0
Input Buffer
V
DD
M
P
X