NEC PD75402A - Manual (Page 71)

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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS
As the PCC is set in 0 by RESET input,
Φ
is reset-started at the slowest speed (state in which the operating voltage
range is wide). For this reason, in a system with a slow supply voltage rise (such as a system with a high- capacitance
capacitor connected), correct operation is possible even when an adequate supply voltage cannot be attained after
a power-on reset.
Table 5-5 Maximum Time Required for Change of CPU Clock
0010 1
0000
0011 1
0000 8
0010 15.3 µ s
0011 8
0000 16
0011
0010 16
PCC Before Change PCC After Change
Max. No. of Machine Cycles
Required for Change of
Φ
Max. Time Required for Change of
Φ
* (When f XX = 4.19 MHz)
* When standby mode is not set until
Φ
changes.
Fig. 5-15 Change of
Φ
after Power-On Reset
5V
0V
Supply
Voltage
RESET Input Signal
CPU
Operation
Oscillator
Stabilization
Time Low-Speed
Operation
Progran
Start Change (By Program)
High-Speed
Operation
Φ