NEC PD75402A - Manual (Page 85)

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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS
(8) INTCSI control circuit
Controls the generation of interrupt requests. In the following case, the interrupt requests (INTCSI) are generated
and interrupt request flags (IRQCSI) are set (see Fig. 6-1 “Interrupt Control Circuit Block Diagram”).
• In 3-wire serial I/O mode
An interrupt request is generated on each count of 8 serial clock cycles.
• In SBI mode
When WUP* = “0” … An interrupt request is generated on each count of 8 serial clock cycles.
When WUP = “1” … An interrupt request is generated when the SVA and SIO values match after address
reception.
* WUP: Wake-up function specified bit (bit 5 of CSIM)
(9) Serial clock control circuit
Controls the supply of the serial clock to the shift register. Also controls the clock output to the SCK pin when
the internal system clock is used.
(10) Busy/acknowledge output circuit, bus release/command acknowledge detection circuit
These circuits perform output and detection of various control signals in the SBI mode.
They do not operate in the 3-wire serial I/O mode.
5.5.3 Register Functions
(1) Serial operating mode register (CSIM)
The format of the serial operating mode register (CSIM) is shown in Fig. 5-25.
CSIM is an 8-bit register which specifies the serial interface operating mode, serial clock, wake-up function, etc.
CSIM is manipulated by 8-bit memory manipulation instructions. The high-order 3 bits can be manipulated bit
by bit using the individual bit names.
Read/write capability differs from bit to bit (see Fig. 5-25). Bit 6 can be tested only, and data written to this bit
is invalid.
Reset input clears this register to 00H.