Zilog Z08470 - Manual (Page 58)

Z80 CPU Instructions UM008007-0715
46
Z80 CPU
User Manual
After the programmer initializes these three registers, any of these four instructions can be
used. The Load and Increment (LDI) instruction moves one byte from the location pointed
to by HL to the location pointed to by DE. Register pairs HL and DE are then automati-
cally incremented and are ready to point to the following locations. The byte counter (i.e.,
register pair BC) is also decremented at this time. This instruction is valuable when the
blocks of data must be moved but other types of processing are required between each
move. The Load, Increment and Repeat (LDIR) instruction is an extension of the LDI
instruction. The same load and increment operation is repeated until the byte counter
reaches the count of zero. As a result, this single instruction can move any block of data
from one location to any other.
Because 16-bit registers are used, the size of the block can be up to 64 KB long
(1KB = 1024 bits) and can be moved from any location in memory to any other location.
Furthermore, the blocks can be overlapping because there are no constraints on the data
used in the three register pairs.
The LDD and LDDR instructions are similar to LDI and LDIR. The only difference is that
register pairs HL and DE are decremented after every move so that a block transfer starts
from the highest address of the designated block rather than the lowest.
Table 9 specifies the op codes for the four block search instructions. The first, CPI (Com-
pare and Increment) compares the data in the Accumulator with the contents of the mem-
ory location pointed to by Register HL. The result of the compare is stored in one of the
flag bits and the HL register pair is then incremented and the byte counter (register pair
BC) is decremented.
Table 8. Block Transfer Group
Destination Source
Register
Indirect
(DE) Register
Indirect
(HL)
(ED)
A0
LDI – Load (DE) → (HL)
Inc HL and DE, Dec BC
(ED)
B0
LDIR, – Load (DE) → (HL)
Inc HL and DE, Dec BC; repeat until BC = 0.
(ED)
A8
LDD – Load (DE) → (HL)
Inc HL and DE, Dec BC
(ED)
B8
LDDR – Load (DE) → (HL)
Dec HL and DE, Dec BC; repeat until BC = 0.
Note: Register HL points to the source; the DE Register points to the destination; the BC Register is a byte counter.