Zilog Z08470 - Manual (Page 35)

UM008007-0715 Memory Speed Control
Z80 CPU
User Manual
23
In Figure 20, the address space is portrayed in hexadecimal notation. Address bit A10 sep-
arates the ROM space from the RAM space, allowing this address to be used for the chip
select function. For larger amounts of external ROM or RAM, a simple TTL decoder is
required to form the chip selects.
Memory Speed Control
Slow memories can reduce costs for many applications. The WAIT line on the CPU allows
the Z80 to operate with any speed memory. Memory access time requirements, which are
covered in the
Memory Read Or Write section on page 9, are most severe during the M1
cycle instruction fetch. All other memory access cycles complete in an additional one half
clock cycle. Hence, it is sometimes appropriate to add one wait state to the M1 cycle so
slower memories can be used.
Figure 21 is an example of a simple circuit that accomplishes this objective. This circuit
can be changed to add a single wait state to any memory access, as indicated in Figure 22.
Figure 20. RAM Memory Space Organization
1 Kbyte ROM
Address:
0000h
03FFh
0400h
04FFFh
256 Bytes RAM