Zilog Z08470 - Manual (Page 30)

Architectural Overview UM008007-0715
18
Z80 CPU
User Manual
The state of IFF1 is used to inhibit interrupts while IFF2 is used as a temporary storage
location for IFF1.
A CPU reset forces both the IFF1 and IFF2 to the reset state, which disables interrupts.
Interrupts can be enabled at any time by an EI instruction from the programmer. When an
EI instruction is executed, any pending interrupt request is not accepted until after the
instruction following EI is executed. This single instruction delay is necessary when the
next instruction is a return instruction. Interrupts are not allowed until a return is com-
pleted. The EI instruction sets both IFF1 and IFF2 to the enable state. When the CPU
accepts a maskable interrupt, both IFF1 and IFF2 are automatically reset, inhibiting fur-
ther interrupts until the programmer issues a new El instruction.
For all of the previous cases, IFF1 and IFF2 are always equal.
The purpose of IFF2 is to save the status of IFF1 when a nonmaskable interrupt occurs.
When a nonmaskable interrupt is accepted, IFF1 resets to prevent further interrupts until
reenabled by the programmer. Therefore, after a nonmaskable interrupt is accepted, mask-
able interrupts are disabled but the previous state of IFF1 is saved so that the complete
state of the CPU just prior to the nonmaskable interrupt can be restored at any time. When
a Load Register A with Register I (LD A, I) instruction or a Load Register A with Register
R (LD A, R) instruction is executed, the state of IFF2 is copied to the parity flag, where it
can be tested or stored.
A second method of restoring the status of IFF1 is through the execution of a Return From
Nonmaskable Interrupt (RETN) instruction. This instruction indicates that the nonmask-
able interrupt service routine is complete and the contents of IFF2 are now copied back
into IFF1 so that the status of IFF1 just prior to the acceptance of the nonmaskable inter-
rupt is restored automatically.
Table 1 is a summary of the effect of different instructions on the two enable flip-flops.
Table 1. Interrupt Enable/Disable, Flip-Flops
Action IFF1 IFF2 Comments
CPU Reset 0 0 Maskable interrupt, INT disabled.
DI Instruction Execution 0 0 Maskable INT disabled.
EI Instruction Execution 1 1 Maskable, INT enabled.
LD A,I Instruction
Execution * * IFF2 → Parity flag.
LD A,R instruction
Execution * * IFF2 → Parity flag.
Note: