Inc ss – Zilog Z08470 User Manual
Page 208
Z80 Instruction Set
UM008007-0715
196
Z80 CPU
User Manual
INC ss
Operation
ss ← ss + 1
Op Code
INC
Operand
ss
Description
The contents of register pair ss (any of register pairs BC, DE, HL, or SP) are incremented.
In the assembled object code, operand ss is specified as follows:
Condition Bits Affected
None.
Example
If the register pair contains
1000h
, then upon the execution of an INC HL instruction, HL
contains
1001h
.
Register
Pair
ss
BC
00
DE
01
HL
10
SP
11
M Cycles
T States
4 MHz E.T.
1
6
1.50
0
0
s
1
1
0
s
0