Zilog Z08470 - Manual (Page 120)

Z80 Instruction Set UM008007-0715
108
Z80 CPU
User Manual
LD (nn), IX
Operation
(nn + 1) ← IXh, (nn) ← IXI
Op Code
LD
Operands
(nn), IX
Description
The low-order byte in Index Register IX is loaded to memory address (nn); the upper order
byte is loaded to the next highest address (nn + 1). The first n operand after the op code is
the low-order byte of nn.
Condition Bits Affected
None.
Example
If Index Register IX contains 5A30h , then upon the execution of an LD ( 4392h ), IX
instruction, memory location 4392h contains number 30h and location 4393h contains
5Ah .
M Cycles T States 4 MHz E.T.
6 20 (4, 4, 3, 3, 3, 3) 5.00
1 1 1 0 1 1 0 1 DD
0 0 0 1 0 0 1 0 22
n
n