Rlc (hl) – Zilog Z08470 User Manual
Page 225
UM008007-0715
Z80 Instruction Description
Z80 CPU
User Manual
213
RLC (HL)
Operation
Op Code
RLC
Operand
(HL)
Description
The contents of the memory address specified by the contents of register pair HL are
rotated left 1 bit position. The contents of bit 7 are copied to the Carry flag and also to bit
0. Bit 0 is the least-significant bit.
Condition Bits Affected
S is set if result is negative; otherwise, it is reset.
Z is set if result is 0; otherwise, it is reset.
H is reset.
P/V is set if parity even; otherwise, it is reset.
N is reset.
C is data from bit 7 of source register.
M Cycles
T States
4 MHz E.T.
4
15 (4, 4, 4, 3)
3.75
CY
7
0
(HL)
1
1
0
1
1
0
0
1
CB
0
0
0
1
0
1
0
0
06