Zilog Z08470 - Manual (Page 137)

UM008007-0715 Z80 Instruction Description
Z80 CPU
User Manual
125
EX (SP), HL
Operation
H
↔
(SP+1), L
↔
(SP)
Op Code
EX
Operands
(SP), HL
Description
The low-order byte contained in register pair HL is exchanged with the contents of the
memory address specified by the contents of register pair SP (Stack Pointer), and the high-
order byte of HL is exchanged with the next highest memory address (SP+1).
Condition Bits Affected
None.
Example
If the HL register pair contains 7012h , the SP register pair contains 8856h , the memory
location 8856h contains byte 11h , and memory location 8857h contains byte 22h , then
the instruction EX (SP), HL results in the HL register pair containing number 2211h ,
memory location 8856h containing byte 12h , memory location 8857h containing byte
70h and Stack Pointer containing 8856h .
M Cycles T States 4 MHz E.T.
5 19 (4, 3, 4, 3, 5) 4.75
1 1 0 1 1 0 1 0 E3