Zilog Z08470 User Manual
Page 269
UM008007-0715
Z80 Instruction Description
Z80 CPU
User Manual
257
Description
Bit b in operand m is reset.
Condition Bits Affected
None.
Example
Upon the execution of a RES 6, D instruction, bit 6 in register 0 is reset. Bit 0 in the D
Register is the least-significant bit.
Bit
b
Register
r
0
000
B
000
1
001
C
001
2
010
D
010
3
011
E
011
4
100
H
100
5
101
L
101
6
110
A
111
7
111
Instruction
M Cycles
T States
4 MHz E.T.
RES r
4
8 (4, 4)
2.00
RES (HL)
4
15 (4, 4, 4, 3)
3.75
RES (IX+d)
6
23 (4, 4, 3, 5, 4, 3)
5.75
RES (lY+d)
6
23 (4, 4, 3, 5, 4, 3)
5.75