Zilog Z08470 - Manual (Page 313)

UM008007-0715 Z80 Instruction Description
Z80 CPU
User Manual
301
INDR
Operation
(HL) ← (C), B ← 131, HL ← HL1
Op Code
INDR
Operands
None.
Description
The contents of Register C are placed on the bottom half (A0 through A7) of the address
bus to select the I/O device at one of 256 possible ports. Register B is used as a byte coun-
ter, and its contents are placed on the top half (A8 through A15) of the address bus at this
time. Then one byte from the selected port is placed on the data bus and written to the
CPU. The contents of the HL register pair are placed on the address bus and the input byte
is written to the corresponding location of memory. Then HL and the byte counter are dec-
remented. If decrementing causes B to go to 0, the instruction is terminated. If B is not 0,
the Program Counter is decremented by two and the instruction repeated. Interrupts are
recognized and two refresh cycles are executed after each data transfer.
When B is set to 0 prior to instruction execution, 256 bytes of data are input.
If B ≠ 0:
If B = 0:
M Cycles T States 4 MHz E.T.
5 21 (4, 5, 3, 4, 5) 5.25
M Cycles T States 4 MHz E.T.
4 16 (4, 5, 3, 4) 4.00
1 1 0 0 1 1 1 1 ED
1 0 1 1 0 0 1 1 BA