Zilog Z08470 - Manual (Page 144)

Z80 Instruction Set UM008007-0715
132
Z80 CPU
User Manual
LDD
Operation
(DE) ← (HL), DE ← DE – 1, HL ← HL– 1, BC ← BC– 1
Op Code
LDD
Operands
None.
Description
This 2-byte instruction transfers a byte of data from the memory location addressed by the
contents of the HL register pair to the memory location addressed by the contents of the
DE register pair. Then both of these register pairs including the Byte Counter (BC) Regis-
ter pair are decremented.
Condition Bits Affected
S is not affected.
Z is not affected.
H is reset.
P/V is set if BC – 1 ≠ 0; otherwise, it is reset.
N is reset.
C is not affected.
Example
If the HL register pair contains 1111h , memory location 1111h contains byte 88h , the DE
register pair contains 2222h , memory location 2222h contains byte 66h , and the BC reg-
M Cycles T States 4 MHz E.T.
4 16 (4, 4, 3, 5) 4.00
1 1 0 0 1 1 1 1 ED
1 0 0 0 0 0 1 1 A8