Zilog Z08470 - Manual (Page 26)

Architectural Overview UM008007-0715
14
Z80 CPU
User Manual
HALT Exit
When a software HALT instruction is executed, the CPU executes NOPs until an interrupt
is received (either a nonmaskable or a maskable interrupt while the interrupt flip-flop is
enabled). The two interrupt lines are sampled with the rising clock edge during each T4
state as depicted in Figure 11. If a nonmaskable interrupt is received or a maskable inter-
rupt is received and the interrupt enable flip-flop is set, then the HALT state is exited on
the next rising clock edge. The following cycle is an interrupt acknowledge cycle corre-
sponding to the type of interrupt that was received. If both are received at this time, then
the nonmaskable interrupt is acknowledged because it is the highest priority. The purpose
of executing NOP instructions while in the HALT state is to keep the memory refresh sig-
nals active. Each cycle in the HALT state is a normal M1 (fetch) cycle except that the data
received from the memory is ignored and an NOP instruction is forced internally to the
CPU. The HALT acknowledge signal is active during this time indicating that the proces-
sor is in the HALT state.
Figure 10. Nonmaskable Interrupt Request Operation
CLK
NMI
MREQ
RD
RFSH
M1
Refresh
M1 Last M Cycle
Last T State
PC A15 –A0
T3 T1 T2 T4 T1