Zilog Z08470 - Manual (Page 142)

Z80 Instruction Set UM008007-0715
130
Z80 CPU
User Manual
LDIR
Operation
(DE) ← (HL), DE ← DE + 1, HL ← HL + 1, BC F
↔
BC – 1
Op Code
LDIR
Operand
B8
Description
This 2-byte instruction transfers a byte of data from the memory location addressed by the
contents of the HL register pair to the memory location addressed by the DE register pair.
Both these register pairs are incremented and the Byte Counter (BC) Register pair is dec-
remented. If decrementing allows the BC to go to 0, the instruction is terminated. If BC is
not 0, the program counter is decremented by two and the instruction is repeated. Inter-
rupts are recognized and two refresh cycles are executed after each data transfer. When the
BC is set to 0 prior to instruction execution, the instruction loops through 64 KB.
For BC ≠ 0:
For BC = 0:
Condition Bits Affected
S is not affected.
Z is not affected.
H is reset.
M Cycles T States 4 MHz E.T.
5 21 (4, 4, 3, 5, 5) 5.25
M Cycles T States 4 MHz E.T.
4 16 (4, 4, 3, 5) 4.00
1 1 0 0 1 1 1 1 ED
1 0 1 0 0 0 1 0 B0