Zilog Z08470 - Manual (Page 140)

Z80 Instruction Set UM008007-0715
128
Z80 CPU
User Manual
LDI
Operation
(DE) ← (HL), DE ← DE + 1, HL ← HL + 1, BC ← BC – 1
Op Code
LDI
Operands
(SP), HL
Description
A byte of data is transferred from the memory location addressed, by the contents of the
HL register pair to the memory location addressed by the contents of the DE register pair.
Then both these register pairs are incremented and the Byte Counter (BC) Register pair is
decremented.
Condition Bits Affected
S is not affected.
Z is not affected.
H is reset.
P/V is set if BC – 1 ≠ 0; otherwise, it is reset.
N is reset.
C is not affected.
Example
If the HL register pair contains 1111h , memory location 1111h contains byte 88h , the DE
register pair contains 2222h , the memory location 2222h contains byte 66h , and the BC
M Cycles T States 4 MHz E.T.
4 16 (4, 4, 3, 5) 4.00
1 1 0 0 1 1 1 1 ED
1 0 0 0 0 0 1 0 A0