Set b, (ix+d) – Zilog Z08470 User Manual
Page 265
UM008007-0715
Z80 Instruction Description
Z80 CPU
User Manual
253
SET b, (IX+d)
Operation
(IX+d)b ← 1
Op Code
SET
Operands
b, (IX+d)
Description
Bit b in the memory location addressed by the sum of the contents of the IX register pair
and the two’s complement integer d is set. In the assembled object code, operand b is spec-
ified as follows:
Condition Bits Affected
None.
Example
If the index register contains
2000h
, then upon the execution of a SET 0, (IX +
3h
)
instruction, bit 0 in memory location
2003h
is 1. Bit 0 in memory location
2003h
is the
least-significant bit.
Bit Tested
b
0
000
1
001
2
010
3
011
4
100
5
101
6
110
7
111
M Cycles
T States
4 MHz E.T.
6
23 (4, 4, 3, 5, 4, 3)
5.75