Ld dd, (nn) – Zilog Z08470 User Manual
Page 113
UM008007-0715
Z80 Instruction Description
Z80 CPU
User Manual
101
LD dd, (nn)
Operation
ddh ← (nn + 1) ddl ← (nn)
Op Code
LD
Operands
dd, (nn)
Description
The contents of address (nn) are loaded to the low-order portion of register pair dd, and the
contents of the next highest memory address (nn + 1) are loaded to the high-order portion
of dd. Register pair dd defines BC, DE, HL, or SP register pairs, assembled as follows in
the object code:
The first n operand after the op code is the low-order byte of (nn).
Condition Bits Affected
None.
Pair
dd
BC
DE
01
HL
10
SP
11
M Cycles
T States
4 MHz E.T.
6
20 (4, 4, 3, 3, 3, 3)
5.00
1
1
0
0
1
1
1
1
ED
0
1
d
1
1
0
d
1
n
n