Zilog Z08470 - Manual (Page 112)

Z80 Instruction Set UM008007-0715
100
Z80 CPU
User Manual
LD HL, (nn)
Operation
H ← (nn + 1), L ← (nn)
Op Code
LD
Operands
HL, (nn)
Description
The contents of memory address (nn) are loaded to the low-order portion of register pair
HL (Register L), and the contents of the next highest memory address (nn + 1) are loaded
to the high-order portion of HL (Register H). The first n operand after the op code is the
low-order byte of nn.
Condition Bits Affected
None.
Example
If address 4545h contains 37h and address 4546h contains A1h , then upon the execution
of an LD HL, ( 4545h ) instruction, the HL register pair contains A137h .
M Cycles T States 4 MHz E.T.
5 16 (4, 3, 3, 3, 3) 4.00
0 0 0 1 0 0 1 1 2A
n
n