Zilog Z08470 - Manual (Page 179)

UM008007-0715 Z80 Instruction Description
Z80 CPU
User Manual
167
INC (IY+d)
Operation
(lY+d) ← (lY+d) + 1
Op Code
INC
Operands
(lY+d)
Description
The contents of Index Register IY (register pair IY) are added to the two’s-complement
displacement integer, d, to point to an address in memory. The contents of this address are
then incremented.
Condition Bits Affected
S is set if result is negative; otherwise, it is reset.
Z is set if result is 0; otherwise, it is reset.
H is set if carry from bit 3; otherwise, it is reset.
P/V is set if (lY+d) was 7Fh before operation; otherwise, it is reset.
N is reset.
C is not affected.
Example
If Index Register IY are 2020h and memory location 2030h contains byte 34h , then upon
the execution of an INC (IY+ 10h ) instruction, memory location 2030h contains 35h .
M Cycles T States 4 MHz E.T.
6 23 (4, 4, 3, 5, 4, 3) 5.75
1 1 1 0 1 1 1 1 FD
0 0 1 0 0 1 1 0 34
d