Zilog Z08470 - Manual (Page 266)

Z80 Instruction Set UM008007-0715
254
Z80 CPU
User Manual
SET b, (IY+d)
Operation
(IY + d) b ← 1
Op Code
SET
Operands
b, (IY + d)
Description
Bit b in the memory location addressed by the sum of the contents of the IY register pair
and the two’s complement displacement d is set. In the assembled object code, operand b
is specified as follows:
Bit Tested b
0 000
1 001
2 010
3 011
4 100
5 101
6 110
7 111
M Cycles T States 4 MHz E.T.
6 23 (4, 4, 3, 5, 4, 3) 5.75
1 1 1 0 1 1 1 1 FD
1 1 0 1 1 0 0 1 CB
d
1 1 b 1 1 0