Zilog Z08470 - Manual (Page 149)

UM008007-0715 Z80 Instruction Description
Z80 CPU
User Manual
137
CPIR
Operation
A – (HL), HL ← HL+1, BC ← BC – 1
Op Code
CPIR
Operands
None.
Description
The contents of the memory location addressed by the HL register pair is compared with
the contents of the Accumulator. During a compare operation, a condition bit is set. HL is
incremented and the Byte Counter (register pair BC) is decremented. If decrementing
causes BC to go to 0 or if A = (HL), the instruction is terminated. If BC is not 0 and A ≠
(HL), the program counter is decremented by two and the instruction is repeated. Inter-
rupts are recognized and two refresh cycles are executed after each data transfer.
If BC is set to 0 before instruction execution, the instruction loops through 64 KB if no
match is found.
For BC ≠ 0 and A ≠ (HL):
For BC = 0 and A = (HL):
M Cycles T States 4 MHz E.T.
5 21 (4, 4, 3, 5, 5) 5.25
M Cycles T States 4 MHz E.T.
4 16 (4, 4, 3, 5) 4.00
1 1 0 0 1 1 1 1 ED
1 0 1 0 1 0 1 0 B1