Zilog Z08470 - Manual (Page 118)

Z80 Instruction Set UM008007-0715
106
Z80 CPU
User Manual
LD (nn), dd
Operation
(nn + 1) ← ddh, (nn) ← ddl
Op Code
LD
Operands
(nn), dd
Description
The low-order byte of register pair dd is loaded to memory address (nn); the upper byte is
loaded to memory address (nn + 1). Register pair dd defines either BC, DE, HL, or SP,
assembled as follows in the object code:
The first n operand after the op code is the low-order byte of a two byte memory address.
Condition Bits Affected
None.
Pair dd
BC 00
DE 01
HL 10
SP 11
M Cycles T States 4 MHz E.T.
6 20 (4, 4, 3, 3, 3, 3) 5.00
1 1 0 0 1 1 1 1 ED
0 1 d 1 1 0 d 0
n
n