Zilog Z08470 - Manual (Page 151)

UM008007-0715 Z80 Instruction Description
Z80 CPU
User Manual
139
CPD
Operation
A – (HL), HL ← HL – 1, BC ← BC – 1
Op Code
CPD
Operands
None.
Description
The contents of the memory location addressed by the HL register pair is compared with
the contents of the Accumulator. During a compare operation, a condition bit is set. The
HL and Byte Counter (register pair BC) are decremented.
Condition Bits Affected
S is set if result is negative; otherwise, it is reset.
Z is set if A equals (HL); otherwise, it is reset.
H is set if borrow from bit 4; otherwise, it is reset.
P/V is set if BC – 1 x 0; otherwise, it is reset.
N is set.
C is not affected.
Example
If the HL register pair contains 1111h , memory location 1111h contains 3Bh , the Accu-
mulator contains 3Bh , and the Byte Counter contains 0001h . Upon the execution of a
CPD instruction, the Byte Counter contains 0000h , the HL register pair contains 1110h ,
the flag in the F Register is set, and the P/V flag in the F Register is reset. There is no
effect on the contents of the Accumulator or address
1111h .
M Cycles T States 4 MHz E.T.
4 16 (4, 4, 3, 5) 4.00
1 1 0 0 1 1 1 1 ED
1 0 0 0 1 0 1 1 A9