Zilog Z08470 - Manual (Page 244)

Z80 Instruction Set UM008007-0715
232
Z80 CPU
User Manual
r identifies registers B, C, D, E, H, L, or A assembled as follows in the object code field:
Description
An arithmetic shift right 1 bit position is performed on the contents of operand m. The
contents of bit 0 are copied to the Carry flag and the previous contents of bit 7 remain
unchanged. Bit 0 is the least-significant bit.
Condition Bits Affected
S is set if result is negative; otherwise, it is reset.
Z is set if result is 0; otherwise, it is reset.
H is reset.
P/V is set if parity is even; otherwise, it is reset.
N is reset.
C is data from bit 0 of source register.
Example
Index Register IX contains 1000h and memory location 1003h contains the following
data.
Register r
B 000
C 001
D 010
E 011
H 100
L 101
A 111
Instruction M Cycles T States 4 MHz E.T.
SRA r 2 8 (4, 4) 2.00
SRA (HL) 4 15 (4, 4, 4, 3) 3.75
SRA (IX+d) 6 23 (4, 4, 3, 5, 4, 3) 5.75
SRA (lY+d) 6 23 (4, 4, 3, 5, 4, 3) 5.75
1 0 1 0 0 0 1 1
7 6 4 1 0 2 5 3