Zilog Z08470 - Manual (Page 152)

Z80 Instruction Set UM008007-0715
140
Z80 CPU
User Manual
CPDR
Operation
A – (HL), HL ← HL – 1, BC ← BC – 1
Op Code
CPDR
Operands
None.
Description
The contents of the memory location addressed by the HL register pair is compared with
the contents of the Accumulator. During a compare operation, a condition bit is set. The
HL and Byte Counter (BC) Register pairs are decremented. If decrementing allows the BC
to go to 0 or if A = (HL), the instruction is terminated. If BC is not 0 and A = (HL), the
program counter is decremented by two and the instruction is repeated. Interrupts are rec-
ognized and two refresh cycles execute after each data transfer. When the BC is set to 0,
prior to instruction execution, the instruction loops through 64 KB if no match is found.
For BC ≠ 0 and A ≠ (HL):
For BC = 0 and A = (HL):
Condition Bits Affected
S is set if result is negative; otherwise, it is reset.
Z is set if A = (HL); otherwise, it is reset.
H is set if borrow form bit 4; otherwise, it is reset.
M Cycles T States 4 MHz E.T.
5 21 (4, 4, 3, 5, 5) 5.25
M Cycles T States 4 MHz E.T.
4 16 (4, 4, 3, 5) 4.00
1 1 0 0 1 1 1 1 ED
1 0 1 0 1 0 1 1 B9