Zilog Z08470 - Manual (Page 198)

Z80 Instruction Set UM008007-0715
186
Z80 CPU
User Manual
ADD HL, ss
Operation
HL ← HL + ss
Op Code
ADD
Operands
HL, ss
Description
The contents of register pair ss (any of register pairs BC, DE, HL, or SP) are added to the
contents of register pair HL and the result is stored in HL. In the assembled object code,
operand ss is specified as follows:
Condition Bits Affected
S is not affected.
Z is not affected.
H is set if carry from bit 11; otherwise, it is reset.
P/V is not affected.
N is reset.
Register
Pair ss
BC 00
DE 01
HL 10
SP 11
M Cycles T States 4 MHz E.T.
3 11 (4, 4, 3) 2.75
0 0 s 0 1 0 s 1