Zilog Z08470 User Manual
Page 53
UM008007-0715
Load and Exchange
Z80 CPU
User Manual
41
instructions begin on page 68.
The parentheses around the HL indicate that the contents of HL are used as a pointer to a
memory location. In all Z80 load instruction mnemonics, the destination is always listed
first, with the source following. The Z80 assembly language is defined for ease of pro-
gramming. Every instruction is self documenting and programs written in Z80 language
are easy to maintain.
In Table 5, some op codes that are available in the Z80 CPU use two bytes. This feature is
an efficient method of memory utilization because 8-, 18-, 24-, or 32-bit instructions are
implemented in the Z80 CPU. Often utilized instructions such as arithmetic or logical
operations are only eight bits, which results in better memory utilization than is achieved
with fixed instruction sizes such as 16 bits.
All load instructions using indexed addressing for either the source or destination location
actually use three bytes of memory, with the third byte being the displacement, d. For
example, a Load Register E instruction with the operand pointed to by IX with an offset of
+8 is written as:
LID E, (IX + 8)
The instruction sequence for this value in memory is shown in Figure 32.
The two extended addressing instructions are also three-byte instructions. For example,
the instruction to load the Accumulator with the operand in memory location
6F32h
is
written as:
LID A, (6F 32h)
The instruction sequence for this value in memory is shown in Figure 33.
Figure 32. Example of a 3-Byte Load Indexed Instruction Sequence
Note:
Op Code
Address A
A+1
A+2
DD
5E
08
Displacement
Operand