Zilog Z08470 - Manual (Page 324)

Z80 Instruction Set UM008007-0715
312
Z80 CPU
User Manual
OTDR
Operation
(C) ← (HL), B ← B – 1, HL ← HL – 1
Op Code
OTDR
Operands
None.
Description
The contents of the HL register pair are placed on the address bus to select a location in
memory. The byte contained in this memory location is temporarily stored in the CPU.
Then, after the byte counter (B) is decremented, the contents of Register C are placed on
the bottom half (A0 through A7) of the address bus to select the I/O device at one of 256
possible ports. Register B can be used as a byte counter, and its decremented value is
placed on the top half (A8 through A15) of the address bus at this time. Next, the byte to
be output is placed on the data bus and written to the selected peripheral device. Then, reg-
ister pair HL is decremented and if the decremented B Register is not 0, the Program
Counter (PC) is decremented by two and the instruction is repeated. If B has gone to 0, the
instruction is terminated. Interrupts are recognized and two refresh cycles are executed
after each data transfer.
When B is set to 0 prior to instruction execution, the instruction outputs 256 bytes of data.
If B ≠ 0:
M Cycles T States 4 MHz E.T.
5 21 (4, 5, 3, 4, 5) 5.25
1 1 0 0 1 1 1 1 ED
1 0 1 1 1 0 1 1 BB
Note: