Z80 Instruction Set
UM008007-0715
94
Z80 CPU
User Manual
LD I,A
Operation
I ← A
Op Code
LD
Operands
I, A
Description
The contents of the Accumulator are loaded to the Interrupt Control Vector Register, I.
Condition Bits Affected
None.
M Cycles
T States
MHz E.T.
2
9 (4, 5)
2.25
1
1
0
0
1
1
1
1
ED
0
1
0
1
1
1
0
0
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