Zilog Z08470 - Manual (Page 19)

UM008007-0715 Timing
Z80 CPU
User Manual
7
RFSH. Refresh (output, active Low). RFSH, together with MREQ, indicates that the lower
seven bits of the system’s address bus can be used as a refresh address to the system’s
dynamic memories.
WAIT. WAIT (input, active Low). WAIT communicates to the CPU that the addressed
memory or I/O devices are not ready for a data transfer. The CPU continues to enter a
WAIT state as long as this signal is active. Extended WAIT periods can prevent the CPU
from properly refreshing dynamic memory.
WR. Write (output, active Low, tristate). WR indicates that the CPU data bus contains
valid data to be stored at the addressed memory or I/O location.
CLK. Clock (input). Single-phase MOS-level clock.
All signals with an overline are active Low. For example, B/W, in which word is active
Low, or B/W, in which byte is active Low.
Timing
The Z80 CPU executes instructions by stepping through a precise set of basic operations.
These operations include:
• Memory read or write
• I/O device read or write
• Interrupt acknowledge

All instructions are a series of basic operations. Each of these operations can take from
three to six clock periods to complete, or they can be lengthened to synchronize the CPU
to the speed of external devices. These clock periods are referred to as time (T) cycles, and
the operations are referred to as machine (M) cycles. Figure 4 shows how a typical instruc-
tion is a series of specific M and T cycles. In Figure 4, this instruction consists of the three
machine cycles M1, M2, and M3. The first machine cycle of any instruction is a fetch
cycle that is four, five, or six T cycles long (unless lengthened by the WAIT signal, which
is described in the next section). The fetch cycle (M1) is used to fetch the op code of the
next instruction to be executed. Subsequent machine cycles move data between the CPU
and memory or I/O devices, and they can feature anywhere from three to five T cycles
(again, they can be lengthened by wait states to synchronize external devices to the CPU).
The following paragraphs describe the timing which occurs within any of the basic
machine cycles.
During T2 and every subsequent automatic WAIT state (TW), the CPU samples the WAIT
line with the falling edge of the clock. If the WAIT line is active at this time, another
Note: