Zilog Z08470 - Manual (Page 15)

UM008007-0715 General Purpose Registers
Z80 CPU
User Manual
3
Two Index Registers (IX and IY). The two independent index registers hold a 16-bit base
address that is used in indexed addressing modes. In this mode, an index register is used as
a base to point to a region in memory from which data is to be stored or retrieved. An addi-
tional byte is included in indexed instructions to specify a displacement from this base.
This displacement is specified as a two’s complement signed integer. This mode of
addressing greatly simplifies many types of programs, especially when tables of data are
used.
Interrupt Page Address (I) Register. The Z80 CPU can be operated in a mode in which
an indirect call to any memory location can be achieved in response to an interrupt. The I
register is used for this purpose and stores the high-order eight bits of the indirect address
while the interrupting device provides the lower eight bits of the address. This feature
allows interrupt routines to be dynamically located anywhere in memory with minimal
access time to the routine.
Memory Refresh (R) Register. The Z80 CPU contains a memory refresh counter,
enabling dynamic memories to be used with the same ease as static memories. Seven bits
of this 8-bit register are automatically incremented after each instruction fetch. The eighth
bit remains as programmed, resulting from an LD R, A instruction. The data in the refresh
counter is sent out on the lower portion of the address bus along with a refresh control sig-
nal while the CPU is decoding and executing the fetched instruction. This mode of refresh
is transparent to the programmer and does not slow the CPU operation. The programmer
can load the R register for testing purposes, but this register is normally not used by the
programmer. During refresh, the contents of the I Register are placed on the upper eight
bits of the address bus.
Accumulator and Flag Registers. The CPU includes two independent 8-bit Accumula-
tors and associated 8-bit Flag registers. The Accumulator holds the results of 8-bit arith-
metic or logical operations while the Flag Register indicates specific conditions for 8-bit
or 16-bit operations, such as indicating whether or not the result of an operation is equal to
0. The programmer selects the Accumulator and flag pair with a single exchange instruc-
tion so that it is possible to work with either pair.
General Purpose Registers
Two matched sets of general-purpose registers, each set containing six 8-bit registers, can
be used individually as 8-bit registers or as 16-bit register pairs. One set is called BC, DE,
and HL while the complementary set is called BC', DE', and HL'. At any one time, the pro-
grammer can select either set of registers to work through a single exchange command for
the entire set. In systems that require fast interrupt response, one set of general-purpose
registers and an Accumulator/Flag Register can be reserved for handling this fast routine.
One exchange command is executed to switch routines. This process greatly reduces inter-
rupt service time by eliminating the requirement for saving and retrieving register contents
in the external stack during interrupt or subroutine processing. These general-purpose reg-