Zilog Z16F2810 User Manual
Page 87
UM018809-0611
ADD Instruction
ZNEO
®
CPU Core
User Manual
71
ADD
Definition
Add
Syntax
ADD dst, src
Operation
dst
dst + src
Description
Add the source operand to the destination operand. Perform signed (two’s-complement) addition.
Store the sum in the destination operand. The contents of the source operand are not affected.
Flags
Flags are set based on the memory destination size, or 32 bits for register destinations.
7
6
5
4
3
2
1
0
C
Z
S
V
B
CIRQE IRQE
*
*
*
*
*
–
–
–
Legend
C
= Set to 1 if the result generated a carry; otherwise set to 0.
Z
= Set to 1 if the result is zero; otherwise, set to 0.
S
= Set to 1 if the result msb is 1; otherwise set to 0.
V
= Set to 1 if an arithmetic overflow occurs; otherwise set to 0.
B
= Set to 1 if the initial destination or source value is 0; otherwise set to 0.
CIRQE
= No change.
IRQE
= No change.
Note: