Zilog Z16F2810 - Manual (Page 198)

UDIV64 Instruction UM018809-0611
182
ZNEO
®
CPU Core
User Manual
UDIV64
Definition
Unsigned 64-bit Divide
Syntax
UDIV dst, src
Operation
dst[63;32]
 Integer Part (dst/src)
dst[31:0]
 Remainder (dst/src)
Description
This instruction performs an unsigned binary divide operation with a 64-bit dividend and 32-bit
divisor.
The destination operand is a 64-bit register pair, RRd, where d is 0 to 15. Register pair RR0 com-
prises ALU registers {R0, R1}, pair RR1 comprises {R1, R2}, and so on up to RR15, which
comprises {R15, R0}. The first register in each pair contains the high-order quad and the second
register contains the low-order quad of the 64-bit value.
The use of register pair RR14 or RR15 conflicts with the Stack Pointer Register R15 and is
not recommended. The use of register pair RR13 or RR14 conflicts with the Frame Pointer
Register R14 if it is in use.
Before the operation, RRd should contain the 64-bit dividend and the src register Rs should con-
tain the 32-bit divisor.
The operation stores the result’s 32-bit unsigned integer part in the high-order quad of the RRd
register pair, and the 32-bit remainder in the low-order quad.
The source register, Rs, is not changed.
There are 3 possible outcomes of the UDIV64 instruction, depending upon the divisor and the
resulting quotient:
Case 1: If the result’s unsigned integer part is less than 4,294,967,296 , then the quotient is
written to RRd[63:32] and remainder is written to RRd[31:0]. Flags are set according to
the result of the operation.
Note: