Zilog Z16F2810 - Manual (Page 74)

Instruction Opcodes UM018809-0611
58
ZNEO
®
CPU Core
User Manual
0000 0011 1111 ssss
aaaa aaaa aaaa aaaa
aaaa aaaa aaaa aaaa
LD addr32, Rs Store memory Quad; 32-bit address.
0000 0100 mmmm mmmm PUSHMLO mask Push multiple registers, R7–R0.
0000 0101 mmmm mmmm PUSHMHI mask Push multiple registers, R15–R8.
0000 0110 mmmm mmmm POPMLO mask Pop multiple registers, R7–R0.
0000 0111 mmmm mmmm POPMHI mask Pop multiple registers, R15–R8.
0000 1000 iiii iiii LINK #uimm8 Link Frame (PUSH R14; LD R14,R15; SUB
R15,#uimm8).
0000 1001 00xx xxxx — Unimplemented
0000 1001 010+ dddd
xxxx xxxx iiii iiii
LD.B (--Rd), #imm8

LD.B (Rd++), #imm8
Store immediate 8 bits with Predecrement/
Postincrement.
0000 1001 011w dddd
iiii iiii iiii iiii
LD.W (Rd), #imm16

LD (Rd), #simm16
Store signed immediate 16 bits to Word or
Quad.
0000 1001 10+w dddd
iiii iiii iiii iiii
LD.W (--Rd), #imm16

LD.W (Rd++), #imm16

LD (--Rd), #simm16
LD (Rd++), #simm16
Store signed immediate 16 bits to Word or Quad
with Predecrement/Postincrement.
0000 1001 1100 dddd
xxxx xxxx iiii iiii
LD.B (Rd), #imm8 Store immediate 8 bits to Byte.
0000 1001 1101 dddd
iiii iiii iiii iiii
iiii iiii iiii iiii
LD (Rd), #imm32 Store immediate 32 bits to Quad.
0000 1001 111+ dddd
iiii iiii iiii iiii
iiii iiii iiii iiii
LD (--Rd), #imm32
LD (Rd++), #imm32 Store immediate 32 bits to Quad with Predecre-
ment/Postincrement.
0000 1010 iiii iiii PUSH.B #imm8 Push immediate 8 bits onto system stack.
0000 1011 ssss dddd LD (Rd), Rs Store register to Quad.
0000 110w iiii iiii PUSH.W #simm8
PUSH #simm8 Push signed immediate 8 bits to Word or Quad
on system stack.
0000 111b ssss dddd LD.B (Rd), Rs
LD.W (Rd), Rs Store register to Byte or Word.
0001 000+ ssss dddd LD (--Rd), Rs
LD (Rd++), Rs Store register to Quad with Predecrement/
Postincrement.
Table 18. ZNEO CPU Instructions Listed by Opcode (Continued)
Opcode Format Instruction, Operands Description