Zilog Z16F2810 - Manual (Page 62)

Interrupts UM018809-0611
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ZNEO
®
CPU Core
User Manual
2. Configure the Interrupt Enable Registers to disable lower priority interrupts.
3. Execute an EI instruction to enable vectored interrupts.
4. Proceed with the interrupt service routine processing.
5. After processing is complete, execute a DI instruction to disable interrupts.
6. Restore the Interrupt Enable Registers values from the stack.
7. Execute an IRET instruction to return from the interrupt service routine.
For information about Interrupt Priority and Interrupt Enable Registers, refer to the ZNEO
Product Specification that is specific to your device.
Software Interrupt Generation
Software can generate a vectored interrupt request directly by writing to the Interrupt
Request Registers in I/O memory. The Interrupt Controller and CPU handle software
interrupts in the same manner as hardware-generated interrupt requests.
To generate a Software Interrupt, write 1 to the appropriate interrupt request bit in the
selected Interrupt Request Register.
Example. The following instruction writes 1 to Bit 5 of Interrupt Request Register 1
(IRQ1SET):
LD R5, #00100000B ; Load mask for bit 5
OR.B IRQ1SET:IODATA, R5 ; Set interrupt request bit 5
If an interrupt at Bit 5 is enabled and there are no higher priority interrupt requests pend-
ing, program control gets transferred to the interrupt service routine specified by the corre-
sponding interrupt vector.
For more information about the Interrupt Controller and Interrupt Request registers, refer
to the ZNEO Product Specification that is specific to your device.
Polled Interrupts
The ZNEO CPU supports polled interrupt processing. Polled interrupts are used when it is
not desirable to enable vectored interrupts for one or more devices. If interrupts are dis-
abled for a device (or globally), no action is taken after the device asserts its IRQ signal
unless software explicitly polls (tests) the corresponding interrupt bit.
Note:
Note: