Udiv – Zilog Z16F2810 User Manual
Page 196
UDIV Instruction
UM018809-0611
180
ZNEO
®
CPU Core
User Manual
UDIV
Definition
Unsigned Divide
Syntax
UDIV dst, src
Operation
src
Remainder (dst/src)
dst
Integer Part (dst/src)
Description
This instruction performs an unsigned binary divide operation with a 32-bit dividend and 32-bit
divisor. The resulting 32-bit unsigned integer part is stored in the destination register. The 32-bit
remainder is stored in the source register.
There are 2 possible outcomes of the UDIV instruction, depending upon the divisor:
Case 1:
If the divisor is nonzero, then the quotient and remainder are written to the desti-
nation and source registers, respectively. Flags are set according to the result of the opera-
tion.
Case 2:
If the divisor is zero, the destination, source, and flags registers are unchanged,
and a Divide-by-Zero system exception is executed.
Flags
7
6
5
4
3
2
1
0
C
Z
S
V
B
CIRQE IRQE
–
*
*
0
0
–
–
–
Legend
C
=
No change.
Z
=
Set to 1 if bits [31:0] of the integer part are zero; otherwise set to 0.
S
=
Set to 1 if bit [31] of the integer part is 1; otherwise set to 0.
V
=
Cleared to 0.
B
=
Cleared to 0.
CIRQE
=
No change.
IRQE
=
No change.