Zilog Z16F2810 User Manual
Page 191
UM018809-0611
TM Instruction
ZNEO
®
CPU Core
User Manual
175
TM
Definition
Test Under Mask
Syntax
TM dst, src
Operation
dst AND src
Description
This instruction tests selected bits in the destination operand for a 0 logical value. Specify the bits
to be tested by setting a 1 bit in the corresponding bit position in the source operand (the mask).
The TM instruction ANDs the value from the destination operand with the source value (mask).
Check the Zero flag can to determine the result. If the
Z
flag is set, all of the tested bits are 0. TM
does not alter the contents of the destination or source.
Flags
Flags are set based on the memory destination size, or 32 bits for register destinations.
7
6
5
4
3
2
1
0
C
Z
S
V
B
CIRQE IRQE
–
*
*
0
*
–
–
–
Legend
C
=
No change.
Z
=
Set to 1 if the result is zero; otherwise, set to 0.
S
=
Set to 1 if the result msb is 1; otherwise set to 0.
V
=
Cleared to 0.
B
=
Set to 1 if the initial destination or source value is 0; otherwise set to 0.
CIRQE
=
No change.
IRQE
=
No change.
Note: