Zilog Z16F2810 - Manual (Page 168)

SDIV Instruction UM018809-0611
152
ZNEO
®
CPU Core
User Manual
SDIV
Definition
Signed Divide
Syntax
SDIV dst, src
Operation
src

Remainder (dst/src)

dst

Integer Part (dst/src)
Description
This instruction performs signed binary divide operation with a 32-bit dividend and 32-bit divi-
sor. The 32-bit integer part is stored in the destination register. The 32-bit remainder is stored in
the source register with the same sign as the dividend.
There are 3 possible outcomes of the SDIV instruction, depending upon the divisor and the
resulting quotient:
Case 1: If the integer part is in the range –2,147,483,648 to +2,147,483,647, then the quo-
tient and remainder are written to the destination and source registers, respectively. Flags
are set according to the result of the operation.
Case 2: If the divisor is zero, the destination, source, and flags registers are unchanged,
and a Divide-by-Zero system exception is executed.
Case 3: If the initial destination value is –2,147,483,648 (8000_0000H) and the initial source
value is –1 (FFFF_FFFFH), the unsigned value 2,147,483,648 (8000_0000H) is written to
the destination register, the source register is cleared, and the Sign and Overflow flags are
set to 1. In this case the Sign flag is incorrect, but the result can be used as an unsigned
value. A Divide Overflow exception is not executed.