Zilog Z16F2810 - Manual (Page 113)

UM018809-0611 DEC Instruction
ZNEO
®
CPU Core
User Manual
97
Examples
Before: R3=FFFF_B024H, FFFF_B02CH=702EH
DEC.W 8(R3) ;Object Code: ADF3 4008
After: FFFF_B02CH=702CH, Flags C, S, Z, V, B=0
Before: FFFF_B034H=2EH
DEC.B B034H:RAM ;Object Code: ADA3 B034
After: FFFF_B034H = 2DH, Flags C, Z, S, V, B =0
DEC soff14(Rd) {ADFH, Rd} {1xB, soff14}
DEC.W addr16 ADA7H addr16
DEC.W addr32 ADB7H addr[31:16] addr[15:0]
DEC.W (Rd) {AC7H, Rd}
DEC.W soff14(Rd) {ADFH, Rd} {01B, soff14}
DEC.B addr16 ADA3H addr16
DEC.B addr32 ADB3H addr[31:16] addr[15:0]
DEC.B (Rd) {AC3H, Rd}
DEC.B soff14(Rd) {ADFH, Rd} {00B, soff14}
Note:
1. The ZNEO CPU assembler uses a SUB opcode to implement DEC Rd. The one-word instruction
ADD Rd, #-1 can be used if ADD Flags behavior is acceptable.
Instruction, Operands Word 0 Word 1 Word 2