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Memory data size, R more information, see the, Section on – Zilog Z16F2810 User Manual

Page 46: More information, see the

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Operand Addressing

UM018809-0611

30

ZNEO

®

CPU Core

User Manual

The ERAM and EROM address space suffixes tell the assembler to use 32-bit addressing,
as shown in the following statements. A full 32-bit address can access external memory or
memory-mapped I/O anywhere in the 4 GB address space.

LD.SB R7, B002H:EROM ; Effective address is 0000_B002H

LD.SB R7, B002H:ERAM ; Effective address is 0000_B002H

The assembler uses memory space mnemonics only to select an appropriate address size
(16 or 32 bit). The assembler does not check an absolute address to make sure it actually
resides in the specified space, but the assembler generates a warning if a label is used in a
space other than the space in which it was declared. See the

Address Space

section on

page 15 for more information about memory spaces.

Memory Data Size

The ZNEO CPU’s default data size is 32 bits (Quad). Any instruction that addresses an 8-
bit or 16-bit value in memory must use a mnemonic suffix to specify the data size. The
previous examples use the ‘.B’ suffix to tell the CPU that only 8 bits (one byte) must be
loaded. The following data size suffixes can be used (using LD as an example):

LD (No Suffix).

Read or write 32 bits (four bytes). In a read, for example, the byte at the

specified effective address loads into bits [31:24] of the destination register. The three sub-
sequent memory bytes load into bits [23:16], [15:8], and [7:0] of the destination register,
in that order.

LD.W.

Read or write 16 bits (two bytes). In an unsigned read, for example, bits [31:16] of

the destination register are cleared, the byte at the specified effective address loads into
bits [15:8] of the register, and the byte at the next (+1) address loads into bits [7:0] of the
register.

LD.B.

Read or write 8 bits (one byte). In an unsigned read, for example, bits [31:8] of the

destination register are cleared, and the byte at the specified effective address loads into
bits [7:0] of the register.

Figure 7

on page 31 displays the mapping of register bytes to memory bytes for different

data sizes. When 8-bit or 16-bit memory is read or written, the high-order bits are filled or
truncated as described in the

Resizing Data

section on page 31.

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