Zilog Z16F2810 - Manual (Page 78)

Instruction Opcodes UM018809-0611
62
ZNEO
®
CPU Core
User Manual
1010 1011 1ooo dddd
iiii iiii iiii iiii
iiii iiii iiii iiii
BOP (Rd), #imm32 Binary operation ‘ooo’ on Quad using immediate
Quad.
1010 1100 0boo dddd UOP.B (Rd)
UOP.W (Rd) Unary operation ‘oo’ on Byte or Word.
1010 1100 1xoo dddd UOP (Rd) Unary operation ‘oo’ on Quad.
1010 1101 0ooo dddd
iiii iiii iiii iiii
BOP (Rd), #simm16 Binary operation ‘ooo’ on Quad using signed
immediate Word.
1010 1101 1000 xxxx — Unimplemented
1010 1101 1001 dddd
xxxx xooo iiii iiii
BOP.B (Rd), #imm8 Binary operation ‘ooo’ on Byte using immediate
Byte.
1010 1101 1010 0boo
aaaa aaaa aaaa aaaa
UOP.B addr16
UOP.W addr16 Unary operation ‘oo’ on Byte or Word. 16-bit
address.
1010 1101 1010 1xoo
aaaa aaaa aaaa aaaa
UOP addr16 Unary operation ‘oo’ on Quad. 16-bit address.
1010 1101 1011 0boo
aaaa aaaa aaaa aaaa
aaaa aaaa aaaa aaaa
UOP.B addr32
UOP.W addr32 Unary operation ‘oo’ on Byte or Word. 32-bit
address.
1010 1101 1011 1xoo
aaaa aaaa aaaa aaaa
aaaa aaaa aaaa aaaa
UOP addr32 Unary operation ‘oo’ on Quad. 32-bit address.
1010 1101 11oo dddd
0brr rrrr rrrr rrrr
UOP.B soff14(Rd)
UOP.W soff14(Rd) Unary operation ‘oo’ on Byte or Word.
1010 1101 11oo dddd
1xrr rrrr rrrr rrrr
UOP soff14(Rd) Unary operation ‘oo’ on Quad.
1010 1110 ssss dddd UDIV Rd, Rs Unsigned Divide, 64-bit result.
1010 1111 ssss dddd SDIV Rd, Rs Signed Divide, 64-bit result.
1011 0000 ssss dddd UMUL Rd, Rs Unsigned Multiply, 64-bit result.
1011 0001 ssss dddd SMUL Rd, Rs Signed Multiply, 64-bit result.
1011 0010 ssss dddd MUL Rd, Rs Unsigned Multiply, 32-bit result.
1011 0011 xxxx xxxx — Unimplemented
1011 0100 ssss dddd SRA Rd, Rs Arithmetic shift right by src bits. Extend modifier
causes shifted-out bits to overwrite src.
1011 0101 ssss dddd SRL Rd, Rs Logical shift right by src bits. Extend modifier
causes shifted-out bits to overwrite src.
Table 18. ZNEO CPU Instructions Listed by Opcode (Continued)
Opcode Format Instruction, Operands Description