Zilog Z16F2810 - Manual (Page 48)

Operand Addressing UM018809-0611
32
ZNEO
®
CPU Core
User Manual
LD.SB R10,7002H
By default, the ZNEO CPU assembler uses an unsigned instruction opcode if the exten-
sion type is not specified for an 8- or 16-bit memory read. The EXT instruction is provided
for extending 8-bit or 16-bit values contained in a register.
The CPU uses ordinary two’s complement notation to represent signed values. In this
notation, the negative of a number is its binary complement, plus one. The most signifi-
cant bit (msb) represents the sign—a one in the msb indicates that the number is negative.
You can use signed or unsigned instructions with a particular memory location. Ensure the
correct usage of extension type whenever a memory location is read.
Table 14 lists data sizes, suffixes, and ranges for signed and unsigned values.
Register-Indirect Memory Addressing
A register-indirect operand uses an address contained in an ALU register, plus an optional
offset, to address data in a memory location.
Example. The following assembly-language statement loads the destination register, R10,
with data from a memory byte pointed to by register R12, plus an offset.
LD.UB R10, 4(R12)
Figure 8 displays this example. It reads a base address value from R12, adds the signed
offset, 4, to create an effective address in memory, and then loads register R10 with the
value at that address. The parentheses indicate a register-indirect operand.
Table 14. Data Sizes for Memory Read
Size Bits
Signed or
Unsigned
Mnemonic Suffix Range (Hex) Range (Decimal)
Byte 8 Unsigned .UB 0 to FF 0 to 255
Signed .SB 80 to FF,
00 to 7F –128 to –1,

0 to 127
Word 16 Unsigned .UW 0 to FFFF 0 to 65,535
Signed .SW 8000 to FFFF,

0000 to 7FFF
–32,768 to –1,

0 to 32,767
Quad 32 Unsigned (none) 0 to FFFF_FFFF 0 to 4,294,967,295
Signed (none) 8000_0000 to
FFFF_FFFF,

0000_0000 to
7FFF_FFFF
–2,147,483,648 to –1,

0 to 2,147,483,647