Instruction cycle time, Instruction fetch cycles – Zilog Z16F2810 User Manual
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Architectural Overview
ZNEO
®
CPU Core
User Manual
5
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All 32 bits of a source or destination ALU Register are used for arithmetic and logical
operations.
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When an 8-bit or 16-bit memory read is performed, the value is extended to 32-bits in
the destination register. Unsigned (zero) or Signed extension can be specified.
•
When an 8-bit or 16-bit memory write is performed, the source register’s value is trun-
cated (only the least significant 8 or 16 bits are stored in memory.)
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The CALL, IRET, LINK, POP, POPM, PUSH, PUSHM, RET, TRAP, and UNLINK
instructions; system interrupts; and exceptions use Register R15 as the Stack Pointer.
If not used, R15 behaves like any other ALU Register.
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The LINK, UNLINK, and some LD operations use Register R14 as a Frame Pointer. If
not used, R14 behaves like any other ALU Register.
Instruction Cycle Time
Instruction cycle times vary from instruction to instruction. Instructions are pipelined
which means the current instruction executes while the next instruction is being fetched.
This allows higher performance at a specific clock speed.
Instruction Fetch Cycles
The following equation is used to calculate the minimum number of cycles required to
fetch an instruction into the CPU:
Fetch Cycles = (bus_wait_states + 1)
opcode_bytes/bus_bytes
In the above equation, the following points are true:
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Bus wait states is configured on a bus to accommodate memory specifications. The
number of wait states is added to each memory read or write on that bus.
For details about wait states, refer to the ZNEO product specification that is specific to
your device .
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The opcode bytes value can be 2, 4 or 6, depending on the instruction. Immediate
operands, if any, are included in the opcode fetch, so they do not affect execution
cycles.
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The bus bytes value can be 1 or 2, for fetches from an 8-bit or 16-bit bus, respectively.
For more details, see the
Note: