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Zilog Z16F2810 User Manual

Page 79

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UM018809-0611

Instruction Opcodes

ZNEO

®

CPU Core

User Manual

63

1011 0110 ssss dddd

SLL Rd, Rs

Logical shift left by src bits. Extend modifier
causes shifted-out bits to overwrite src.

1011 0111 ssss dddd

RL Rd, Rs

Rotate left by src bits.

1011 100i iiii dddd

SRA Rd, #uimm5

Arithmetic shift right by uimm bits. Extend modi-
fier causes shifted-out bits to overwrite src.

1011 101i iiii dddd

SRL Rd, #uimm5

Logical shift right by uimm bits. Extend modifier
causes shifted-out bits to overwrite src.

1011 110i iiii dddd

SLL Rd, #uimm5

Logical shift left by uimm bits. Extend modifier
causes shifted-out bits to overwrite src.

1011 111i iiii dddd

RL Rd, #uimm5

Rotate left by uimm bits.

1100 rrrr rrrr rrrr

JP rel12

Jump with 12-bit offset.

1101 rrrr rrrr rrrr

CALL rel12

Call with 12-bit offset.

1110 cccc rrrr rrrr

JP cc, rel8

Conditional Jump, signed 8-bit offset.

1111 0000 rrrr rrrr

rrrr rrrr rrrr rrrr

JP rel24

Jump with 24-bit offset.

1111 0001 rrrr rrrr

rrrr rrrr rrrr rrrr

CALL rel24

Call with 24-bit offset.

1111 0010 0000 ssss

JP (Rs)

Jump to address pointed to by src.

1111 0010 0001 ssss

CALL (Rs)

Call address pointed to by src.

1111 0010 0010 cccc

rrrr rrrr rrrr rrrr

JP cc,rel16

Conditional Jump, 16-bit offset.

1111 0010 0011 0000

iiii iiii iiii iiii

iiii iiii iiii iiix

JPA #imm32

Jump to immediate address.

1111 0010 0011 0001

iiii iiii iiii iiii

iiii iiii iiii iiix

CALLA #imm32

Call immediate address.

1111 0010 0011 001x

Unimplemented

1111 0010 0011 01xx

Unimplemented

1111 0010 0011 1xxx

Unimplemented

1111 0010 01xx xxxx

Unimplemented

1111 0010 1xxx xxxx

Unimplemented

1111 0011 xxxx xxxx

Unimplemented

Table 18. ZNEO CPU Instructions Listed by Opcode (Continued)

Opcode Format

Instruction, Operands

Description

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