Zilog Z16F2810 - Manual (Page 17)

UM018809-0611 Architectural Overview
ZNEO
®
CPU Core
User Manual
1
Architectural Overview
Zilog’s ZNEO CPU meets the continuing demand for faster and more code-efficient
microcontrollers. ZNEO CPU’s architecture greatly improves the execution efficiency of
code developed using higher-level programming languages like ‘C’ language.
Features
The key features of ZNEO CPU architecture include:
•
Highly efficient register-based architecture with sixteen 32-bit registers. All register
operations are 32 bits wide
•
Up to 4 GB linear address space (16 MB on current devices) with multiple internal
and external memory and I/O buses
•
Short 16-bit addressing for internal RAM, I/O, and 32K of nonvolatile memory
•
Instructions using memory can operate on 8-bit, 16-bit, or 32-bit values
•
Support for 16-bit memory paths (internal and external)
•
Pipelined instruction fetch, decode, and execution
•
Bus arbiter supports simultaneous instruction and memory access (when possible)
Other features of the ZNEO CPU include:
•
Direct register-to-register architecture allows each 32-bit register to function as an
accumulator. This improves the execution time and decreases the memory required for
programs.
•
Expanded stack support:
– Push/Pop instructions use one 32-bit register as Stack Pointer
– Single-instruction push and pop of multiple registers
– Stack Pointer overflow protection
– Predecrement/postincrement Load instructions simplify the use of multiple stacks
– Link and Unlink operations with enhanced Frame Pointer-based instructions for
efficient access to arguments and local variables in subroutines
•
Program Counter overflow protection
•
User-selectable bus bandwidth control for DMA and CPU sharing